This application is related to Korean Application No. 2000-46094, filed Aug. 9, 2000, the disclosure of which is hereby incorporated herein by reference.
The present invention generally relates to integrated circuit devices, and more particularly, to sense amplifiers.
Recently, in accordance with a trend towards high performance and miniaturization, the operating speed of semiconductor memory devices has been significantly increased, while the overall size of these devices has been reduced. Sensing and amplifying data stored in these memory devices is typically one of the main functions performed by these devices. Thus, since most semiconductor memory devices use analog techniques for sensing data, it is highly desirable to optimize a sensing method for use in conjunction with these high speed semiconductor memory devices.
A conventional data amplifier typically has a fixed gain during normal operation of the semiconductor device. Some conventional data amplifiers may have a gain that varies with the operation mode of the semiconductor device. Thus, it is difficult to provide a stable output waveform due to changes in the level and phase of the input potential provided to a data amplifier. In general, the frequency band of a data amplifier is on the order of hundreds of megahertz (MHz). Therefore, input potential and impedance need to be appropriately considered. If a mismatch between these factors exists, the output gain may be reduced and/or the output waveform may oscillate. Thus, the operating speed of a semiconductor device may be degraded and invalid data may result. Furthermore, as the size of these semiconductor devices continues to be reduced, the distance between transmission lines of input signals will typically become closer, which could cause the occurrence of noise due to crosstalk between adjacent transmission lines, thus, increasing the possibility of outputting invalid data.
Integrated circuit memory devices according to embodiments of the present invention include a sense amplifier having a pair of differential input signal lines, a pair of differential output signal lines and a current amplifier. The current amplifier has an input stage electrically coupled to the pair of differential input signal lines and an output stage electrically coupled to the pair of differential output signal lines. The input stage and/or the output stage may be responsive to a first control signal that reduces a gain of the current amplifier when the first control signal is asserted.
In further embodiments of the present invention the input stage of the current sense amplifier may include a load circuit that is electrically coupled to the pair of differential input signal lines and a first reference signal line. The load circuit may be responsive to the first control signal and a second control signal. During a sense and amplify time interval, an impedance of a load provided by the load circuit to the pair of differential input signal lines may increase from a first level when the second control signal is being asserted and the first control signal is not being asserted to a second level, higher than the first level, when the first and second control signals are both being asserted.
In other embodiments of the present invention, the output stage may include an enable circuit that is electrically coupled to the pair of differential output signal lines and a second reference signal line. The enable circuit may be responsive to the first control signal and an enable signal. During a sense and amplify time interval, an impedance of a load provided by the enable circuit to the pair of differential output signal lines may increase from a third level when the enable signal is being asserted and the first control signal is not being asserted to a fourth level, higher than the third, level when the first control signal and enable signal are both being asserted.
In still further embodiments of the present invention the output stage may include a stabilizer circuit that is electrically coupled to the pair of differential output signal lines and a third reference signal line. The stabilizer circuit may be responsive to the first control signal. During a sense and amplify time interval, an impedance of a load provided by the stabilizer circuit to the pair of differential output signal lines may increase from a fifth level to a sixth level when the first control signal is being asserted.